The design of processor-based systems may include designing a design block that communicates with a processor via an interface bus of the processor. An example design block is a bridge between the protocol of the processor's interface bus and another communication protocol, such as Ethernet. An example processor is the IBM Power PC processor which is included in the Virtex-II Pro and Virtex-4 families of programmable logic devices (PLD) available from Xilinx, Incorporated. Another example processor is the Microblaze processor that may be implemented in the programmable logic and routing resources of a PLD. The IBM Power PC processor of Xilinx PLDs has the interface buses of IBM CoreConnect, including the Processor Local Bus, the On-Chip Peripheral Bus, and the Device Control Register bus. The Microblaze processor has the On-Chip Peripheral Bus for an interface bus.
The development of a design block for a processor-based system may include testing the design block using simulation of an example processor-based system. However, a simulation that includes a simulation of a processor may have a slow simulation speed due to the complexity of simulating the processor. In addition, the testing of a design block may require issuing particular transactions on the interface bus, and the processor may provide indirect control of the transactions issued on the interface bus, which may make the testing of a design block time-consuming and expensive. The testing of a design block may require issuing certain transactions on the interface bus that a specific normally functioning processor cannot issue, such as certain transactions with aborts, retries, and/or errors including bus parity errors.
A bus functional model may be a simplification of a processor that allows a direct specification of the transactions issued on the interface bus by the bus functional model. The bus functional model may also provide explicit control of exceptional conditions, such as aborts, retries, and errors. A simulation of a processor-based system using a bus functional model instead of a processor may have improved simulation speed. The bus functional model may also check every protocol rule of the interface bus and flag any violations of these protocol rules.
For a design block that is coupled to an interface bus of a processor and a second bus, a bus functional model could be used to control the interface bus, except that testing of the design block may require coordinated control and validation of both buses. For example, a defect in the design block may not cause improper operation on the processor's interface bus because the improper operation may only be evident on the second bus. Coordination of control and validation for a design block having a processor's interface bus and another bus may be time-consuming and expensive.
The present invention may address one or more of the above issues.